1. Technical Field
The present disclosure represents a computer aided design (CAD) tool that is capable of generating plasma charging metal design rules for MOS transistors of integrated circuits (IC) in a plasma-based manufacturing process. The generated plasma charging metal design rules are used by circuit designers in chip design to protect the transistors from damages incurred during the manufacturing process.
2. Description of Related Art
Plasma process induced charging damages in gate oxide of transistors has long been a reliability concern in semiconductor industry. Such damage sometimes can cause failure in an entire product line during manufacturing process, incurring significant operating loss for business. The plasma charging phenomena are rather complicated because of involvement of many factors. For example, although the conditions of the plasma sources can obviously inflict the damage to transistor gate oxides, the process parameters and the internal and external physical features of the transistor itself can cause gate oxide damages as well in some cases even during a normal operating condition of a plasma source.
As the feature size or the transistors continue to scale down, the huge network of the interconnect metals that connect billions of the transistors in integrated circuit (IC) chips nowadays can inevitably absorb a large amount of plasma-induced charges during one patterning process for the interconnect metal. As a result, improper design of the interconnect layout can potentially introduce excessive charges into the transistors in some regions of the IC chips, incurring damage on the transistors and failing the entire chip product.
Therefore in the modern-day IC chip design, design-manufacturing interaction induced chip failure such as the above plasma charging-related interconnect failure in products are challenges facing the designers. The above plasma-interconnect interaction induced manufacturing yield problem may be tackled by the approach of process recipe adjustment. However, the room for such solution may be limited particularly when a corresponding process technology has been beyond its development stage and moved into production where process recipes mostly remain unchanged and a large scale of process adjustment could be quite costly in term of time and operation budget. Thus, adjustment to the chip design appears to be a better solution to be considered. Design for manufacturing (DFM) has become the mainstream in solving such manufacturing issue. Thus, accuracy of the plasma-charging related backend metal design rules is critical to ensure a sound charging-free or minimized interconnect metal layout design and improve the whole yield the end products.
Preparing the backend plasma charging design rules has largely relied on test-structure approach in which transistor test structures to evaluate the plasma-induced charging effect are designed and fabricated on wafers and experiments with measurements are consequently carried out to extract the safe criteria of the backend metal design in order to shield the transistors from the plasma process induced charging damage. Such effort is not only time consuming (in months as usual) but also inefficient as the number of the test structures need to be designed into the test-chip wafers is limited. By using a physics-driven model-based design rule methodology approach, this disclosed transistor plasma charging metal design rule generator is not subject to the above problems and able to generate the plasma charging design rules in a more swift fashion (e.g., within a day).